Planarized selective tungsten metallization system

ABSTRACT

In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

This application is a continuation of application .Iadd.Ser. No.08/134,151, filed Oct. 8, 1993, now abandoned, which is a reissue ofSer. No. 07/383,304, filed Jul. 18, 1989, now U.S. Pat. No. 5,055,423,which is a continuation of .Iaddend.Ser. No. 07/138,239, filed Dec. 28,1987, now abandoned.

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to metal interconnects forintegrated circuits, and more particularly to methods for forminginterconnects by the selective deposition of tungsten and theinterconnects formed thereby.

BACKGROUND OF THE INVENTION

Tungsten metallization by chemical vapor deposition (CVD) hasreliability advantages over metallization using aluminum alloys, and CVDtungsten has lower resistivity and better step coverage than tungstenapplied by sputtering. CVD tungsten is however generally difficult toetch with good selectivity to layers of resist and oxide. Further, thethick CVD tungsten lines required to achieve low sheet resistance aredifficult to planarize with deposited oxide following CVD tungstenpatterning and etching.

Recently, a planar multilevel tungsten interconnect technology has beendeveloped in the industry. Following formation of the device and gatelevel interconnect structures, a dielectric is applied and the surfaceis made planar ("planarized"). Then contact holes are defined and etchedin the dielectric using conventional techniques. These are then filled,for example, using selective chemical vapor deposited (CVD) tungsten.Then more dielectric is deposited, to a thickness equal to the desiredmetal thickness. The dielectric is coated with Si₃ N₄ ("nitride"), andgrooves are lithographically defined where metal interconnect lines aredesired. The nitride is then etched, as well as the dielectric which wasdeposited over the contacts that had been filled with metal. The waferis then implanted with silicon using an ion acceleration, using thenitride as a mask. The nitride is then removed chemically, leavinggrooves where the metal is to be deposited, and heavy silicon dosageonly at the bottom of the grooves.

Selective CVD tungsten is then deposited, the deposition occurring onlyin the grooves where the heavy silicon concentration is present. Thusthe grooves are filled with tungsten to a thickness equal to the depthof the groove. This technique eliminates the problem of tungstenetching, and leaves filled the spaces between tungsten metal lines.

The following problems exist with this conventional process. A siliconimplantation step of sufficient dosage to support selective CVD tungstendeposition is relatively expensive to perform. The adhesion of tungstento, for instance, silicon-implanted oxide, is not expected to be good.In addition, the etching of the grooves in the dielectric must beperformed without endpoint, leaving open the possibility of etchinggrooves into underlying circuitry. Finally, the nucleation preference ofsilicon over the surrounding oxide is not optimum.

From the above, it can be seen that a need has arisen in the industryfor an improved planarized selective tungsten metallization system.

SUMMARY OF THE INVENTION

According to one aspect of the invention, an integrated circuitcomprises a base structure and a first thick dielectric layer formed onthe base structure. A plurality of contact holes are formed atpreselected locations through the first dielectric layer to the basestructure. A thin nucleation layer, selected such that a preselectedmetal will preferentially nucleate thereon, is formed on the outersurface of the first dielectric layer, and further on the sidewalls andbottom of the contact holes. This layer is defined lithographically withthe desired lead pattern for the next metallization level, and etched,either using wet or dry etching techniques. A second thick dielectriclayer is formed over the first dielectric layer and the nucleationlayer. Then, grooves are formed through the second dielectric layer toexpose the patterned nucleation layer.

Preferably, the preselected metal comprises tungsten and the nucleationlayer comprises a thin (<150 nm) layer of titanium-tungsten alloy, or abilayer of sputtered titanium and tungsten. It is also preferred thatthe nucleation layer be formed on the bottom and sides of the orifice.

According to yet another aspect of the invention, the planar dielectricis formed on the base structure, and then a thin nucleation layer isdeposited and patterned in a lead pattern for the next metallizationlead, with the exception that the resist is removed over locations wherethe metallization layer should make contact to the underlying basematerial. In other words, this patterning step uses a singlelithographic mask level which leaves resist on the metallization linesbut removes it from the lines where contacts are to be cut through thedielectric underneath. The metal is etched, and the resist is removed.Then a dielectric layer is applied to the surface at a thickness equalto the desired thickness of selective tungsten metallization to be used.Grooves are then patterned and etched over the thin metallization linesinto which the selective tungsten is to be deposited. The grooves arelithographically defined in such a way that all of the dielectric abovethe metal is exposed to the subsequently-performed etch, as well as thedielectric above contact holes defined in the thin metal, mentionedabove. Then an anisotropic dielectric etch is performed which createsgrooves where the metallization lines will be, and which clean theunderlying metal. An etchant is used which etches dielectric at anextremely high rate in comparison with the thin metal. This etch reachesan endpoint upon hitting the thin metal layer. The etch is thencontinued on a timed basis until the contact holes between themetallization layer being formed and the base material are etched. Thisaspect of the invention therefore involves one less lithographicpatterning step than the first aspect adduced herein.

The sidewalls of the contacts under the thin nucleating metal layer maybe coated with metal in order to improve the selective depositionprocess. This is to be accomplished by sputter depositing very thinmetal and coating it with a planarizing film such as photoresist. Thisfilm can then be removed in such a way as to expose only the top of themetal-coated dielectric film and the sidewalls of the grooves over thethin metal layer first defined. This removal can be accomplished bymeans of an oxygen plasma in the case of a photoresist film. The metalso exposed is removed in a wet etchant, such as H₂ O₂. The remainingplanarizing film used to protect the metal at the bottom of the groovesand in the contacts, is removed such as by means of an oxygen plasma.This leaves a groove which is coated with metal only at the bottom, withcontact holes protruding downwardly from the groove bottom. The contactholes have sidewalls and bottom coated with metal.

This structure is then subjected to selective CVD tungsten deposition inorder to fill the grooves and the contacts, forming a fully planarmetallization system.

The use of the planarized selective tungsten metallization system ofthis invention provides several advantages. First, a siliconimplantation step is replaced by a cheaper thin nucleation layerdeposition and definition. Since the nucleation layer preferablycomprises a metal such as titanium tungsten alloy, an end point to theetch of the dielectric layer can be performed.

In conventional processes, it is difficult to control the line width ofCVD tungsten, and overetching the tungsten causes a serious rougheningof the multi-level oxide. In the present invention, it is not necessaryto etch the thick CVD tungsten layers, as is also the case in the recentinterconnect technology already described. By conventional processes, itis also difficult to deposit CVD oxide in such a way that voids are notformed between the metal lines, causing step coverage problems in thenext metal level. The method of the present invention provides a furtheradvantage in that the oxide is deposited before the thick metal isdeposited, greatly reducing oxide step coverage and voiding problems.

Furthermore, in conventional processes, CVD oxide is deposited over themetal leads and subsequently planarized by the etch back of a smoothspin-on coating such as photoresist or spin-on glass. This providesshort range planarization only. The present invention produces true,global planarization because no spin-on sacrificial layer is required.Instead grooves are etched and refilled with metal keeping the surfaceplanar at all steps.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects of the invention and their advantages will be discernedwith reference to the following Detailed Description in conjunction withthe appended drawings, in which:

FIGS. 1a-1c are schematic isometric views of a small section of anexemplary integrated circuit, showing successive steps in a firstembodiment of a metallization process according to the invention;

FIGS. 2a-2c are isometric views corresponding to FIGS. 1a-1c, showingsuccessive steps in a second embodiment of a metallization processaccording to the invention;

FIGS. 3a-3d are isometric views corresponding to FIGS. 1a-1c or 2a-2c,showing successive steps in a third embodiment of a metallizationprocess according to the invention; and

FIGS. 4a-4d are schematic sectional views of steps in a fabricationprocess according to a fourth embodiment of the invention.

DETAILED DESCRIPTION

A first embodiment of the process according to the invention is shown inFIGS. 1a-1c, which are successive isometric views showing steps in thefabrication of an exemplary integrated circuit. Referring first to FIG.1a, a base layer 10 is first provided. Base layer 10 can be a siliconsemiconductor substrate as shown, but it can also be a more complexstructure. Layer 10 may for example be a partially formed integratedcircuit structure having one or more structures fabricated out ofpolycrystalline silicon, such as a polysilicon emitter contact.

In the exemplary embodiment, a gate 12, as can be formed of polysilicon,has already been fabricated to be insulatively disposed over layer 10 bya gate oxide layer 14. FIGS. 1a-1c are an exemplary demonstration of howa first level of contact and interconnect metallization is madeaccording to the invention to gate 12 and also to an area 16 of thesubstrate layer 10. While only two first-level contacts to layer 10 andgate 12 are shown, it should be understood that in actual practice amultitude of first-level contacts will be formed to a very large numberof integrated circuit devices that have been previously fabricated in oron layer 10.

A first, thick dielectric layer 18 is formed over layer 10. Layer 18 mayalternatively constitute multiple layers (not shown) of silicon dioxideand/or other dielectric materials. Layer 18 is deposited and thenplanarized by the deposition and etchback of a sacrificial planarizingspin-on coating (not shown). Layer 18 may further include a top layer ofborophosphosilicate glass (BPSG, not shown).

After the deposition and planarization of multilevel oxide layer 18, aplurality of contact holes 20 are patterned and etched down to layer 10or gate 12. The photoresist (not shown) is then stripped and the contactholes 20 are refilled with tungsten plugs 22 using selective CVDtungsten deposition. A layer 23 of platinum silicide may first bedeposited, patterned and etched inside contact holes 20, with the plugs22 thereafter selectively nucleating on the platinum silicide layers 23.The tungsten will selectively nucleate on the polysilicon gate 12 orsubstrate area 16 (or, where employed, PtSi layers 23) as opposed tomultilevel oxide layer 18. The difference in the height between the twoplugs 22 occurs because of the thickness of gate 12 and gate oxide layer14. This completes the contact metallization in this embodiment.

Turning now to FIG. 1b, a very thin, preferably metallic nucleationlayer 24 is next deposited over an outer surface 26 of layer 18, andalso over plugs 22. Layer 24 is then patterned and etched in a secondmetallization pattern to form individual nucleation layers 28. As willbe shown, nucleation layers 28 each are formed the bottom of respectiveorifice or slot. Each nucleation layer 28 is shown to, but does notnecessarily need to, extend laterally completely around the upperperimeter of each plug 22 to which layer 28 connects. Any number ofmetals can be used to fabricate nucleation layers 28, includingtitanium, sputtered tungsten, chromium, any of the other transitionmetals, aluminum, or silicon. A preferred material is titanium-tungstenalloy, since this yields superior adhesion and high temperaturestability characteristics. Another preferred material is a bilayer ofsputtered titanium and tungsten.

Turning now to FIG. 1c, the remaining steps in fabricating aninterconnect according to the first embodiment of the invention areshown. A thick multilevel second dielectric layer 30, such asphosphosilicate glass (PSG), is patterned in a reverse interconnectmetallization pattern (not shown) so as to define orifices or slots 32that each correspond to a nucleation layer 28. The second dielectriclayer 30 is then etched back down to nucleation layers 28 to createorifices or slots 32.

A layer of photoresist (not shown) that was used to pattern and etchholes 32 is then removed by ashing or by solvent cleanup. Then, tungstenis deposited by selective chemical vapor deposition in orifices or slots32 to form metal interconnect conductors 34. The CVD tungsten depositionstep is carried on until the top or outer surface 36 of interconnectconductors 34 is at least substantially coplanar with the top or outersurface 38 of PSG layer 30. The surfaces 36 and 38 may be fairly rough,and the FIGURES are in this respect quite schematic. By the use of"substantially coplanar" it is meant that the smoothed averages ofsurfaces 36 and 38 lie in as nearly the same plane as is practicable.The substantially planarized surface formed by surfaces 36 and 38 maythen have a layer of oxide (not shown) deposited on it to complete thestructure. The process can then be repeated to form additionalmetallization layers starting with via patterning and etching.

A second and particularly preferred embodiment of the process accordingto the invention is shown in FIGS. 2a through 2c, which illustratesuccessive steps in fabricating a greatly simplified and exemplaryintegrated circuit structure like that shown in FIGS. 1a-1c. ThroughoutFIGS. 1a-1c, 2a-2c, 3a-3d and 4a-4d, like numbers identify like partswhere possible.

As before, a first dielectric layer 18 is deposited over a basestructure 10, a gate 12 and a gate oxide layer 14. Layer 18 isplanarized as described for FIG. 1a. Preferably, a nitride layer 50 isthen deposited as the last dielectric layer of multilevel dielectriclayer 18. Contact holes 20 are patterned and etched through thedielectric layers 18 and 50. A nucleating conductors 52 are thendeposited, patterned and etched to conform to an interconnectmetallization pattern, and further to coat the interior of contact holes20. Nucleating conductors 52 can be formed of any of the materials givenfor nucleation layers 28 (FIG. 1b), but are preferably fabricated oftitanium-tungsten alloy (Ti-W). The Ti-W nucleating conductors 52 coverboth the sidewalls 53 of contact holes 20 and the bottom 55 thereof.Nucleating conductors 52 also cover a surface 56 of nitride layer 50 inthe areas immediately adjoining contact holes 20, as well as in thoseother areas of surface 56 that will be the bottom of the orifices orslots (58; see FIG. 2b) for the interconnect conductors. The overlap ofthe contact edges by the thin nucleating conductors 52 is not required,however.

Turning now to FIG. 2b, a second, preferably phosphosilicate glass (PSG)dielectric layer 30 is deposited on nitride layer 50 and on nucleatingconductors 52. Before the etch, dielectric layer 30 will fill orifices54 inside contact holes 20. Dielectric layer 30 is then patterned usinga reverse interconnect metallization pattern (not shown).

An etch of dielectric layer 30 is performed that uses a reverseinterconnect metallization pattern to etch through layer 30 to thenucleation conductors 52 and adjacent areas of surface 56 of nitridelayer 50. The interposition of hard mask layer 50 prevents caving oneither side of each nucleating conductor 52 during an isotropic (wet)contact clearing and groove widening etch after the grooves are cut.Nitride layer 50 is also used as an etch stop for an isotropic (wet)contact clearing etch once the grooves are first cut. A small,intentional overetch is performed in this embodiment of layer 30 inorder to assure the removal of all dielectric material out of contactholes 54. The etch creates a plurality of slots or orifices 58 intowhich the tungsten will be selectively deposited.

Turning now to FIG. 2c, tungsten is deposited by chemical vapordeposition into orifices 54 and slots 58, preferentially nucleating onTi-W conductors 52. The CVD continues until integral contact andinterconnect tungsten conductors 60 have been accumulated with outersurfaces 62 that are substantially coplanar with the outer surface 38 ofsecond dielectric layer 30. This planarized surface is then ready forfurther levels of metallization or for an oxide passivation layer.

The above-described second embodiment is particularly advantageous inthat it produces a plurality of integral combination contact andinterconnect conductive leads 60. The number of interfaces between thesecond level metal and the first level device contacts are minimized,and this in turn reduces metallization resistance.

FIGS. 3a-3d illustrate a third embodiment of the invention where it isdesired to save a masking step. As shown in FIG. 3a, a substrate orintegrated circuit layer 10 is once again provided having a polysilicongate 12 and an oxide layer 14 deposited thereon. As before, a firstdielectric layer 18 is deposited over substrate 10, polysilicon gatelayer 12 and oxide layer 14.

First nucleation layers 70 are then deposited on surface 26 of firstdielectric layer 18, patterned in what is principally an interconnectmetallization pattern, and etched. In addition, wherever a contactbetween the base structure and the interconnect metal is desired to bemade, each first nucleation layer 70 will be patterned and etched tohave defined therethrough an orifice 72 that will be used to self-aligna subsequent etch step for forming a respective contact hole.

Turning now to FIG. 3b, a second thick dielectric layer 30 is nextdeposited over first nucleation layers 70 and first dielectric layer 18.Dielectric layer 30 is then patterned with a reverse interconnectmetallization pattern (not shown) that is somewhat smaller in itslateral dimensions that nucleation layers 70. This reverse metallizationpattern, however, omits a reverse mask for orifices 72 (FIG. 3a). Whenthe etchant is applied, slots or orifices 74 will be formed in seconddielectric layer 30 down to nucleation layers 70. Within orifices 72(FIG. 3a) the etch will continue downward past first nucleation layers70 through first dielectric layer 18 to create a respective plurality ofcontact holes 76.

For the selective CVD tungsten step, a nucleation layer should be formedin the bottoms of orifices 76. If this formation is omitted, it ispossible that lateral selective tungsten growth from the edges of metal70 would pinch off the top of the contact holes 76 before a continuousconductor can be formed in the contact holes 76. Therefore, a secondnucleation layer 78 is preferably deposited over the outer surface ofdielectric layer 30 and to coat the sidewalls 80 of slots 74, thebottoms 82 (indicated in phantom) of slots 74, the sidewalls 84 ofcontact holes 76, and the bottoms 86 of contact holes 76. This secondnucleation layer 78 is preferably made of the same materials as firstnucleation layer 70.

Referring next to FIG. 3c, a resist layer 88 is deposited overnucleation layer 78. Resist layer 88 is ashed back to surface 90 in eachslot 74 that is slightly above the bottom surface of slots 74. An etchof nucleation layer 78 is then performed to remove those areas of secondnucleation layer 78 above the surfaces 90 of remaining resist portions88. The remaining portions of nucleation layer 78 will be entirelywithin slots 74 and contact holes 76. The remaining resist portions 88are then removed.

Referring next to FIG. 3d, the structure is ready for the selectivedeposition of combination contact and interconnect tungsten conductors92. As in the preferred embodiment shown in FIGS. 2a-2d, conductors 92form integral contact and interconnect metallization since the tungstenextends down from any slot 74 into all contact holes 76 connectedthereto. Tungsten conductors 92 are selectively deposited until theirouter surfaces 94 are substantially coplanar with the outer surface 38of second dielectric layer 30.

A fourth embodiment is shown in FIGS. 4a-4d, which are sectional viewsof sequential fabrication steps like those shown in the other FIGURES.

In a fourth embodiment according to the invention, alternate dielectricmaterials are used in a way that makes self-aligned contacts with anextra interposed thin dielectric film instead of with an extrainterposed thin metal film. In this approach, three or more alternatinglayers of two dielectric materials that can be etched with selectivelyto each other are deposited on top of the base structure.

FIGS. 4a-4d are schematic, highly magnified sectional views illustratingan exemplary process according to this fourth embodiment. Referringfirst to FIG. 4a, a dielectric stack comprising a first, thick silicondioxide layer 18, an alumina layer 100, and a second, thick silicondioxide layer 102 are sequentially deposited on a base structure 10. Inthe illustrated embodiment, the layers 18 and 102 are approximately 1.0microns in thickness, while alumina layer 100 is approximately 0.2microns thick.

A resist layer 104 is next deposited on SiO₂ layer 102 and is patternedwith a contact pattern to create an orifice 106. SiO₂ layer 102 is thenetched within orifice 106 with selectivity to underlying Al₂ O₃ layer100. Resist layer 104 is then stripped.

Referring next to FIG. 4b, a second resist layer 108 is deposited onlayer 102 and within orifice 106. Resist layer 108 is then patternedwith an inverse interconnect pattern. FIG. 4b illustrates the case wherethere is a misalignment between the contact pattern and the interconnectpattern, such that a portion 110 of resist layer 108 is left withincontact orifice 106. This misalignment results in a smaller contactorifice 111. That portion of Al₂ O₃ layer 100 that is exposed both byorifice 106 and the interconnect-patterned resist layer 108 (orifice111) is etched with selectivity to the underlying oxide 18 as well asoxide layer 102.

Referring next to FIG. 4c, the same interconnect-patterned resist layer106 is used in an etch of SiO₂ layer 102 with selectivity to Al₂ O₃layer 100. At the same time that the exposed areas of oxide layer 102are etched, the exposed areas of first oxide layer 18 is etched withinorifice 111 to create a contact hole 112. The etch of exposed areas ofsecond oxide layer 102 creates a slot 114 for the interconnect metal.The interconnect-patterned resist layer 108 is then stripped.

Referring finally to FIG. 4d, contact hole 112 and slot 114 are filledto a top surface 116 of layer 102 by the selective deposition oftungsten. One method of accomplishing this is to form a layer 118 ofTi-W alloy on the bottoms and sidewalls of contact hole 112 and slot114. Layer 118 would then be etched back so that only a small portion ofsidewalls 120 of slot 114 would be covered, per the technique describedfor FIGS. 3a-3d. Layer 118 would then be used as a nucleation layer forthe selective chemical vapor deposition of tungsten to form integralinterconnect structure 122.

If necessary, the resist layer used to etch back layer 118 could bepatterned with a relatively uncritical pattern to assure that thenucleation metal 118 remains in the bottom of large interconnectfeatures.

In an alternative embodiment (not shown), one to three additional thinalternating layers of Al₂ O₃ and SiO₂, or other dielectrics with similarselective etch properties with respect to each other, can be added in asimilar sequence to avoid patterning the interconnect pattern over adeep etch contact hole. In this last alternative, the pattern would betransferred from the resist into thinner, top layers of Al₂ O₃ and SiO₂.The pattern would then be transferred from these thin layers to thickerlayers of SiO₂ in subsequent etch steps. Further, the order of etchingcontacts or interconnects can be exchanged in some schemes with morethan three alternating layers of SiO₂ and Al₂ O₃.

While the invention has been particularly described as employing CVDtungsten it has application to any metal that can be selectivelydeposited by CVD on a conductive nucleation layer.

In summary, an improved selective metallization system has been shownand described. The system uses a nucleation layer, preferably a singlelayer as formed in the orifices of contact holes and extending over thebottoms of interconnect orifices or slots, with a metal such as tungstenbeing selectively deposited on the nucleation layer thereafter. Thepresent invention provides technical advantages in that it results in aplanarized upper surface of the second dielectric layer, avoids theforming of voids in the dielectric layers, and provides a nucleationlayer having low resistance and a high quality of adhesion.

While illustrated embodiments of the present invention have beendescribed in the above Detailed Description, the invention is notlimited thereto but only by the spirit and scope of the appended claims.

What is claimed is:
 1. A process for forming a conductiveinterconnection in an integrated circuit structure, comprising the stepsof:providing a partially formed integrated circuit having a substratestructure; forming a first .[.thick.]. insulating layer on saidsubstrate; forming at least one contact hole through said insulatinglayer.Iadd., exposing a portion of said substrate.Iaddend.; depositing a.[.thin.]. nucleation layer on said first insulating layer.Iadd.,wherein said nucleation layer is formed at least on the outer surface ofsaid first insulating layer, the sidewalls of said contact hole and onthe exposed portion of said substrate, while leaving at least a portionof said contact hole voided.Iaddend.; patterning said .[.thin.].nucleation layer; forming a second .[.thick.]. insulating layer on saidfirst insulating layer and said patterned .[.thin.]. nucleation layer;forming an opening in said second insulating layer to expose saidpatterned .[.thin.]. nucleation layer; and selectively depositing aconductor in said opening, said patterned .[.thin.]. nucleation layerserving as a nucleation site for said selective deposition.
 2. Theprocess of claim 1 wherein said opening in said second insulating layeris formed by etching said second insulating layer, said .[.thin.].nucleation layer serving as an etch stop for said etching. .[.3. Theprocess of claim 1 further comprising the step of filling said contacthole with a conductive material prior to said depositing of said thinnucleation layer..]..[.4. The process of claim 3 wherein said step offilling said contact hole comprises the steps of:forming a contactnucleation layer of said substrate at the bottom of said contact hole;and selectively depositing a conductive material in said contact holeusing said contact nucleation layer as a nucleation site..].5. Theprocess of claim .[.3.]. .Iadd.1, .Iaddend.wherein said .[.thinnucleation layer covers the walls of said contact hole and covers theexposed portion of said substrate, said.]. selective depositionfill.[.ing.]..Iadd.s .Iaddend.said contact hole.
 6. The process of claim1 wherein said .[.thin.]. nucleation layer comprises a Titanium-Tungstenalloy and said conductor comprises Tungsten.
 7. A process for forming aconductive interconnection in an integrated circuit structure,comprising the steps of:providing a partially formed integrated circuithaving a substrate structure; forming a first .[.thick.]. insulatinglayer on said substrate; depositing a .[.thin.]. nucleation layer onsaid first insulating layer; patterning said .[.thin.]. nucleationlayer, said patterned nucleation layer having a contact opening exposingsaid first .[.thick.]. insulating layer for formation of a contact hole;forming a second .[.thick.]. insulating layer on said first insulatinglayer and said patterned .[.thin.]. nucleation layer; forming an etchmask .[.for patterning.]. .Iadd.on .Iaddend.said second insulatinglayer; etching said second insulator layer using said etch mask toprovide an opening in said second .[.thick.]. insulating layer, saidopening exposing .Iadd.at least .Iaddend.said .Iadd.contact opening insaid .Iaddend.patterned .[.thin.]. nucleation layer; forming saidcontact hole in said first insulating layer using said .[.thin.].nucleation layer and said etch mask .[.to.]. as a pattern for etchingsaid first insulating layer; .Iadd.forming a second nucleation layer onsaid nucleation layer and in said contact hole; .Iaddend. selectivelydepositing a conductor in said opening, said patterned .[.thin.].nucleation layer serving as a nucleation site for said selectivedeposition.
 8. The process of claim 7 wherein said opening in saidsecond insulating layer is formed by etching said second insulatinglayer, said .[.thin.]. nucleation layer serving as an etch stop for saidetching.
 9. The process of claim 7 wherein said .[.thin.]. nucleationlayer comprises a Titanium-Tungsten alloy and said conductor comprisesTungsten.
 10. A process for forming a conductive interconnection in anintegrated circuit structure, comprising the steps of:providing apartially formed integrated circuit having a substrate structure;forming a first .[.thick.]. insulating layer on said substrate;depositing a etch stop layer on said first insulating layer; patterningsaid etch stop layer, said patterned etch stop layer having a contactopening exposing said first .[.thick.]. insulating layer for formationof a contact hole; forming a second .[.thick.]. insulating layer on saidfirst insulating layer and said etch stop layer; forming an etch mask.[.for patterning.]. .Iadd.on .Iaddend.said second insulating layer;etching said second insulating layer using said etch mask to provide anopening in said second .[.thick.]. insulating layer, said openingexposing .Iadd.at least .Iaddend.said .Iadd.contact opening in saidpatterned .Iaddend.etch stop layer; forming said .[.contact.]. hole insaid first insulating layer using said etch stop layer and said etchmask .[.to.]. as a pattern for etching said first insulating layer;forming a .[.thin.]. nucleation layer on said etch stop layer and insaid contact hole; and selectively depositing a conductor in saidopening, said patterned .[.thin.]. nucleation layer serving as anucleation site for said selective deposition.
 11. The process of claim10 wherein said opening in said second insulating layer is formed byetching said second insulating layer, said etch stop layer serving as anetch stop for said etching.
 12. The process of claim 10 wherein said.[.thin.]. nucleation layer comprises a Titanium-Tungsten alloy and saidconductor comprises Tungsten. .Iadd.13. The process of claim 1, whereinsaid nucleation layer comprises a bilayer. .Iaddend..Iadd.14. Theprocess of claim 1, wherein said nucleation layer is sufficiently thinto assist in maintaining a substantially planarized upper surface ofsaid second insulating layer. .Iaddend..Iadd.15. The process of claim 1,wherein said second insulating layer is sufficiently thick to assist inmaintaining a substantially planarized upper surface of said secondinsulating layer. .Iaddend..Iadd.16. The process of claim 1, whereinsaid second insulating layer is sufficiently thick and said nucleationlayer is sufficiently thin to assist in maintaining a substantiallyplanarized upper surface of said second thick insulating layer..Iaddend..Iadd.17. The process of claim 1, and further comprising thestep of depositing a second nucleation layer on said nucleation layerafter said step of forming an opening, such that said second nucleationlayer serves as a nucleation site for said selective deposition..Iaddend..Iadd.18. The process of claim 17, wherein said nucleationlayer serves as an etch stop for said step of forming an opening..Iaddend..Iadd.19. A process for forming a conductive interconnection inan integrated circuit structure, comprising the steps of:forming a firstinsulating layer on a substrate; depositing a nucleation layer on saidfirst insulating layer; patterning said nucleation layer, said patternednucleation layer having a contact opening exposing said first insulatinglayer; forming a second insulating layer on said first insulating layerand said patterned nucleation layer; forming an opening in said secondinsulating layer to expose at least said contact opening in saidpatterned nucleation layer; forming a hole in said first insulatinglayer using said nucleation layer and said second insulating layer as apattern for etching said first insulating layer; depositing a secondnucleation layer on said nucleation layer and in said hole after saidstep of forming an opening; and selectively depositing a conductor insaid opening, said second nucleation layer serving as a nucleation sitefor said selective deposition. .Iaddend..Iadd.20. A process for forminga conductive interconnection in an integrated circuit structure,comprising the steps of:forming a first insulating layer on a substrate;depositing an etch stop layer on said first insulating layer; patterningsaid etch stop layer, said patterned etch stop layer having a contactopening exposing said first insulating layer; forming a secondinsulating layer on said first insulating layer and said patterned etchstop layer; forming an opening in said second insulating layer to exposeat least said contact opening in said patterned etch stop layer; forminga hole in said first insulating layer using said etch stop layer andsaid second insulating layer as a pattern for etching said firstinsulating layer; depositing a nucleation layer on said etch stop layerafter said step of forming an opening; and selectively depositing aconductor in said opening, said nucleation layer serving as a nucleationsite for said selective deposition. .Iaddend..Iadd.21. A process forforming a conductive interconnection in an integrated circuit structure,comprising the steps of: providing a partially formed integrated circuithaving a substrate structure; forming a first insulating layer abovesaid substrate; forming at least one contact hole through saidinsulating layer, wherein said contact hole has sidewalls and exposes aportion of said substrate; depositing a nucleation layer above saidfirst insulating layer, wherein said nucleation layer is formed at leaston the outer surface of said first insulating layer, on the sidewalls ofsaid contact hole and on the exposed portion of said substrate, whileleaving at least a portion of said contact hole voided; patterning saidnucleation layer; forming a second insulating layer above said firstinsulating layer and said patterned nucleation layer; forming an openingin said second insulating layer to expose said patterned nucleationlayer; and selectively depositing a conductor in said opening, saidnucleation layer serving as a nucleation site for said selectivedeposition. .Iaddend..Iadd.2. A process for forming a conductiveinterconnection in an integrated circuit structure, comprising the stepsof:providing a partially formed integrated circuit having a substratestructure; forming a first insulating layer on said substrate; formingat least one contact hole through said insulating layer, wherein saidcontact hole has sidewalls and exposes a portion of said substrate;depositing a nucleation layer on said first insulating layer, whereinsaid nucleation layer is formed at least on the outer surface of saidfirst insulating layer, on the sidewalls of said contact hole and on theexposed portion of said substrate, while leaving at least a portion ofsaid contact hole voided; patterning said nucleation layer; forming asecond insulating layer above said first insulating layer and saidpatterned nucleation layer; forming an opening in said second insulatinglayer to expose said patterned nucleation layer; and selectivelydepositing a conductor in said opening, said nucleation layer serving asa nucleation site for said selective deposition. .Iaddend..Iadd.23. Theprocess of claim 22, wherein said nucleation layer is sufficiently thinto assist in maintaining a substantially planarized upper surface ofsaid second insulating layer. .Iaddend..Iadd.24. The process of claim22, wherein said second insulating layer is sufficiently thick to assistin maintaining a substantially planarized upper surface of said secondinsulating layer. .Iaddend..Iadd.25. The process of claim 22, whereinsaid second insulating layer is sufficiently thick and said nucleationlayer is sufficiently thin to assist in maintaining a substantiallyplanarized upper surface of said second insulating layer..Iaddend..Iadd.26. A process for forming a conductive interconnection inan integrated circuit structure comprising the steps of:providing apartially formed integrated circuit having a substrate structure;forming a first insulating layer above a substrate; forming at least onecontact hole through said insulating layer, wherein said contact holehas sidewalls and exposes a portion of said substrate; depositing anucleation layer above said first insulating layer, wherein saidnucleation layer is formed at least on the outer surface of said firstinsulating layer, on the sidewalls of said contact hole and on theexposed portion of said substrate, while leaving at least a portion ofsaid contact hole voided; patterning said nucleation layer; forming asecond insulating layer above said first insulating layer and saidpatterned nucleation layer; and forming an opening in said secondinsulating layer to expose said patterned nucleation layer; andselectively depositing a conductor in said opening, said patternednucleation layer serving as a nucleation site for said selectivedeposition. .Iaddend..Iadd.27. A process for forming a conductiveinterconnection in an integrated circuit structure comprising the stepsof: forming a first insulating layer above a substrate; depositing anucleation layer above said first insulating layer; i patterning saidnucleation layer, said patterned nucleation layer having a contactopening exposing said first insulating layer; forming a secondinsulating layer above said first insulating layer and said patternednucleation layer; and forming an opening in said second insulating layerto expose at least said contact opening in said patterned nucleationlayer; i forming a hole in said first insulating layer using saidpatterned nucleation layer and said second insulating layer as a patternfor etching said first insulating layer; depositing a nucleation layeron said patterned nucleation layer and in said hole and after said stepof forming an opening; and selectively depositing a conductor in saidopening, said patterned nucleation layer serving as a nucleation sitefor said selective deposition. .Iaddend..Iadd.28. A process for forminga conductive interconnection in an integrated circuit structure,comprising the steps of:providing a partially formed integrated circuithaving a substrate structure; forming a first insulating layer on saidsubstrate; forming at least one contact hole through said insulatinglayer, wherein said contact hole has sidewalls and exposes a portion ofsaid substrate; depositing a first nucleation layer on said firstinsulating layer, wherein said nucleation layer is formed at least onthe outer surface of said first insulting layer, on the sidewalls ofsaid contact hole and on the exposed portion of said substrate, whileleaving at least a portion of said connection hole voided; patterningsaid first nucleation layer; forming a second insulating layer on saidfirst insulating layer and said patterned first nucleation layer;forming an opening in said second insulating layer to expose saidpatterned first nucleation layer; depositing a second nucleation layeron said first nucleation layer after said step of forming an opening;and selectively depositing a conductor in said opening, said secondnucleation layer serving as a nucleation site for said selectivedeposition. .Iaddend.